1. Field of the Invention
The present invention relates to priority control systems for determining rights to bus use for performing direct data transfer between the random access memory (RAM) of an information processor and periphery equipment without using the central processing unit (CPU).
2. Description of the Prior Art
For DMA transfer bus interrupts, there are two cases; one in which rights to bus use by the CPU are prioritized in a main group and the other in which a priority order is determined for a subgroup of a requesting source in the main group.
A conventional priority control system is shown in FIG. 3. The priority control system includes a CPU 1; a dynamic memory or RAM 2; four input/output (I/O) devices 3; a data bus 4; an address bus 5; and a direct memory access (DMA) controller 7.
The DMA controller 7 includes a sampling signal generator 6; a priority circuit 8; a priority encoder 9; an access controller 10; and a DRAM controller 11. The RAM requires periodic refreshing. The priority circuit 8 determines a priority order among bus requests. The priority circuit 8 for performing main sampling is composed of a circuit in which an interrupt priority order is determined by hardware. The priority encoder 9 for determining a priority order among channels of the I/O devices 3 is composed of a circuit for performing auxiliary sampling. For example, the priority encoder 9 has four channel input ports, of which one channel is given priority and outputted as a bus request to a predetermined channel of the priority circuit 8. The I/O devices 3 consist of four circuit periphery devices, for example, which are connected to respective channel input ports of the priority encoder 9. The priority order from top to bottom in the priority circuit 8 is as follows: (1) RAM refreshing request by the DRAM controller 11; (2) HOLD external interrupt request; (3) DRQ bus request by the I/O devices 3; and (4) bus requests by the CPU 1. Consequently, there are a main priority group connected to the priority circuit 8 and a auxiliary priority group within the I/O devices 3 which is one of the inputs to the priority circuit 8. The sampling signal generator 6 outputs a machine cycle basic clock to the priority circuit 8 and a sampling signal 2 having a frequency of a half of the machine cycle to the priority encoder 9. Gates 1-1, 1-2, 10-1, 10-2, 11-1, and 11-2 interconnect the buses 4 and 5 to the respective controllers. DMACK is a response signal to the I/O chip of a bus requesting source, etc. to which priority is given.
The operation will be described with reference to FIG. 4. The basic clock .phi. synchronized with the machine cycle, for example, and the half clock 2.phi. made by dividing the basic clock by 2 are inputted to the sampling signal generator 6. Consequently, DRQL and DRQH are outputted in synchronism with "H" of .phi. in the periods "H" and "L" of 2.phi., respectively. The DRQL and DRQH are inputted to the priority encoder 9 and the priority circuit 8, respectively. The priority encoder 9 samples DMA requests DRQs from the respective I/O devices in synchronism with the rising edge of DRQL to select a request of the highest priority and outputs it as a bus request BRQ to the priority circuit 8. The priority circuit 8 samples the bus request BRQ, etc. in synchronism with the rising edge of DRQH, accepts the BRQ if there is neither DRAM refreshing request a nor HOLD request b which are given higher priorities than the BRQ, and outputs a BAK signal, turning off the gates 1-1 and 1-2 which have connected the buses 4 and 5 to the CPU 1 and on the gates 10-1 and 10-2 connected to the access controller (DMAC) 10 to start bus control by the DMAC 10. When the DMAC 10 connects the I/O devices 3 and the RAM 2 by bus control, a signal DMACK for selecting a chip to which the highest priority is given by the priority encoder 9 is outputted to a predetermined I/O device 3 for effecting a DMA transfer.
However, when the BUSY signal is "H" at the main sampling time DRQH, the DMAC 10 is unable to receive the bus use right so that it must wait until the BUSY signal becomes "L". Consequently, the period between the first sampling at the auxiliary sampling signal DRQL and the time when the DMAC 10 resumes the bus use can be so long as shown by A in FIG. 4 that the information becomes too old; that is, it is not the latest DMA request from another I/O device 3.